The fundamental purpose in providing a cache memory closely coupled to a central processing unit (CPU) is to enhance the rate that the CPU can receive instructions and operand data and return modified operand data. A cache memory is typically organized to store instructions and operand data as memory lines. Each such memory line may contain multiple instructions interspersed with their corresponding operand data. Since most high-performance CPUs are implemented using a pipelined, multiple-unit architecture, contentions may arise as competing instruction fetch and operand data transfers occur. Such contention occurs most often when both instructions and operand data cache memory accesses are concurrently attempted. The operand access request is normally given priority. Contention also arises whenever an instruction fetch attempt is made following an operand data fetch directed to the same memory line and where there is the possibility that the fetched operand data will be modified. The operand fetch typically locks, or makes private, the memory line until the potentially modified operand data can be returned. If the operand data has in fact been modified, the memory line into which it is stored must typically be written back to mainstore before the instruction fetch may be allowed to proceed as part of the public/private memory line management scheme.
A split-cache architecture is used to alleviate the contention for instructions and data residing in a single cache memory. The split-cache architecture described in the related application identified above further alleviates the throughput degradation that arises from the need to repeatedly write memory lines back to mainstore by tracking the storage of image copies of memory lines in separate instruction and operand data cache buffers. Management of identical memory lines stored in respective instruction and operand data buffers (a "line-pair") is permitted by storing a line-pair status bit and location pointer data in the system address and status information tag associated with each memory line kept in the split-cache. Potentially modified operand data memory lines that are a member of a line-pair are stored back to both the instruction and operand data memory line buffers in replacement of any prior image copy. Thus, with respect to its associated CPU, the split-cache essentially eliminates instruction/operand contention for memory lines stored in the cache.
Another source of cache memory line contention arises in multiple CPU data processing system architectures. Typically, a system controller is implemented to supervise and coordinate the overall operation of the multiple CPU system. Since separate CPUs may be operating on the same potentially modifiable operand data, a primary function of the system controller is to ensure that, at most, only one operand buffer contains a private copy of a memory line. Further, the system controller must operate to ensure that any request for a non-modifiable, public image of an operand data line is taken from the most recently modified version of that memory line wherever it exists in the data processing system. In conventional systems, the system controller is therefore required to access the operand buffer of every CPU's split-cache in order to determine whether and where any private copy of the requested memory line exists. Consequently, the system controller creates contention, resulting in a significant degree of CPU throughput degradation, whenever the system controller accesses or attempts to access the split-cache operand data buffer of any CPU.
One method of avoiding system controller contention for access to the operand data buffers of each of the split-caches is to provide a secondary system address and status information tag store. This secondary tag store is the cumulative equivalent of each tag store maintained as part of the respective split-caches within the data processing system. The system controller thus needs only to consult its secondary tag store to determine the public or private line state of any memory line present outside of mainstore. The secondary tag store is continuously updated by the system controller as it supervises each memory line transfer between mainstore and any CPU split-cache or between any set of CPU split-caches.
Unfortunately, a serious data integrity management problem arises as a result of relying on a secondary tag store rather than on the information contained in the primary tag store of each split-cache. Since the transfer of a memory line can be unexpectedly aborted at any time prior to finally updating a primary split-cache tag store, the system controller must update the secondary tag store synchronously with each and every split-cache memory line transfer or risk losing track of the actual existence of memory lines throughout the data processing system. This requirement places a severe constraint on the design of conventional data processing systems, particularly in terms of data processing throughput. The system controller needs to be able to reliably proceed with the processing of memory line transfer requests after initiating each one and before a prior initiated transfer necessarily completes. Therefore, the system controller must either contend for access to all of the split-cache memory line buffers in a verification process or implement some other mechanism for ensuring memory line data integrity throughout the multiple CPU data processing system.